1. Field of the Invention
The present invention relates to an architecture for display controllers. More specifically, the present invention relates to an architecture for Twisted Nematic Liquid Crystal Display (TN-LCD) controllers embedded in microcontrollers.
2. Background
The present invention is typically provided in a microcontroller-type integrated circuit, but can also be provided in any other type of integrated circuit-driven display panel, especially passive Twisted Nematic Liquid Crystal Displays (TN-LCD). These kind of display panels are well known and can be found in many electronic devices, especially in battery powered devices such as watches, games, basic displays in cameras, etc.
When powered by batteries, the electronic device must reduce its consumption as much as possible to improve the battery lifetime. Therefore, reduced power modes of operation have been designed. For example, when only one static image must be displayed, the powered circuitry can be limited to the display panel itself and the minimum logic circuitry necessary to generate the required signals, rather than powering the entire microcontroller logic including the microprocessor.
Another example is the blinking mode where the image is periodically blanked. This mode can be implemented in different ways resulting in different power consumptions. For a simple LCD panel having a single common backplane terminal, if the segment signals and backplane have the same waveform, the pixels are not visible (not energized), but the signals are toggling and, therefore, some current flows in parasitic capacitances that are inherent to any digital circuitries. The present invention prevents the LCD terminals from this switching during the blank period, thereby reducing the power consumption for the blank period.
However, this power consumption reduction is not important for these single backplane LCD panels. For example, when using LCD panels for basic scientific calculators (for example, a 8×40 dot panel is used in order to display characters using 7×5 dot fonts) or small/basic images/icons, there are not 8×40 (320) terminals in the LCD panel or in the controller driving it because of the resulting associated cost for the integrated circuit packages. These kind of panels use the well known multiplexed technique.
This multiplexing technique involves special waveforms that require signals to be slightly energized even if pixels of the image are not visible. Additionally, intermediate voltage levels must be available for these special waveforms. In order to generate these intermediate voltages, a resistor ladder is often used, which consumes DC current.
The present invention provides circuitry that prevents the terminals of the LCD panel from switching during the period the image is blanked. This prevention is achieved by setting these terminals to logic 0, thereby eliminating the need for any intermediate voltage. As a result, the resistor ladder activity can be disabled. The power consumption is reduced in this mode of operation (blinking).
FIG. 1 represents a simple microcontroller with an LCD display controller. Microcontroller 100 comprises a microprocessor 101 configured to access peripheral circuitries like timers 105, UART 106, and LCD controller 107. The data exchanges are performed by means of the system bus 120, which comprises (not shown) a read data bus carrying data from peripherals to microprocessor 101, a write data bus carrying data from microprocessor 101 to peripherals, an address bus and control signals to indicate transfer direction on system bus 120. Since the address bus of the system bus 120 is shared by all the peripherals, there is a need to decode the value carried on this bus to select one peripheral at a time. A circuitry 102 acts as an address decoder by receiving the address bus (part of system bus 120), and provides select signals 121, 122, 123, 124, and 125. These select signals will be read by peripheral circuits, such as on-chip memories 103, interrupt controller 104, timers 105, UART 106, and LCD controller 107, in order to take into account values carried on system bus 120. Timers 105 may be connected to interrupt controller 104 by line 126. Microcontroller 100 may further comprise clock terminal 143 and reset terminal 144.
On-chip memories 103 allows for the storage of the application software processed by microprocessor 101. Microcontroller 100 is powered by means of a different set of terminals 140 and 141. Terminals 140 comprise a series of physical access terminals (PADs), some for providing VDD and some for providing GND. Terminals 140 power the main parts of the microcontroller 100, including microprocessor 101, address decoder 102, on-chip memories 103, interrupt controller 104, timers 105, and UART 106. Terminal 141 powers the LCD display controller 107. The boundary for the different power supplies is represented by dotted line 150.
The LCD display controller 107 may be the only circuitry to be powered in microcontroller 100 for power consumption considerations. This LCD display controller 107 can drive an LCD panel 108 by means of line 127 and terminals 142. In order to display an image, the software located in on-chip memory 103 is fetched by microprocessor 101 by means of read accesses performed on system bus 120.
The on-chip memory 103 is selected (signal 123 is active) as soon as the address value of the address bus matches the address range allocated for the on-chip memory 103. The address decoder 102 is designed accordingly. The memory 103 provides the corresponding data onto system bus 120, which is read by microprocessor 101 and processed accordingly.
The image to display on a twisted nematic passive LCD panel can be considered as a bit stream, one bit for each LCD dot. If the number of dot exceeds the system bus 120 data size, several accesses will be required to transfer the full image contained in on-chip memory 103 to display controller 107. Therefore, the display controller 107 must contain an image buffer that can be fully loaded by decoding different access on the system bus 120 when the associated select signal 125 is active.
When the microprocessor 101 is instructed to load an image into display controller 107, write accesses are performed on system bus 120. As soon as all write accesses have been performed, there is nothing more to do for the microprocessor 101 and, therefore, it can be powered off. For example, just after having finished transferring the image, the microprocessor 101 can perform an access into UART module 106, which would be externally connected (not shown) to a companion chip to manage the power of the microcontroller 100. For example, the companion chip would receive through RXD/TXD connections a data that would instruct the regulator driving terminals 140 (VDD/GND) to switch off.
FIG. 2 provides the architecture details of display controller 107. The display controller circuitry 200 is connected to the system bus 224 to receive and provide data to the microprocessor. A first buffer of data (“user holding buffer”) 204, connected to system bus 224, comprises a series of registers to store the bit stream for the image to display. These registers can be loaded with the data value carried on system bus 224 only if the address bus carries a specific value (one for each register). Therefore, there is a need for an internal address decoder (not shown, but different from address decoder 102 in FIG. 1).
The display controller circuitry 200 also comprises a second buffer of data (“display frame buffer”) 205, which is connected to user holding buffer 204 contains a copy of the bit stream that is stored in data buffer 204. Loading the frame buffer 205 with the content of the user holding registers is automatically performed by timing generation circuitry 202 asserting signal 231.
The display controller 200 comprises configuration registers 211 that can be accessed at different addresses than the user holding registers. Configuration registers 211 provide the mode of operations 201 of the display controller, which can include, but is not limited to, the blinking frequency signals “LCDBLKFREQ” and the display mode “DISPMODE” which can allow for addressing different types of LCD panels (1, 2, 3, 4 COMMON TERMINAL PANELS).
Considering the blinking mode, the displayed data results in two periods: one period with an energized image according to the bit stream located in the display frame buffer 205 and the other period where all dots are blanked. Therefore, the timing generation circuitry 202 provides a toggling signal 223, which clears the output of the multiplexer 207 when it is low (logical 0) and passes the output of multiplexer 207 when it is high (logical 1). It is possible to achieve this behavior by means of a set of AND gates 206.
The display controller 200 uses the multiplexing technique to provide data to LCD panel. Therefore, both internal buffers are organized accordingly. There are as many outputs as common to address in the LCD panel for each buffer. The multiplexed LCD panel consists of a series of terminals organized as a matrix. There are several common terminals usually called “COMMON.” Each of these common terminals access several other terminals called “SEGMENT” of the LCD panels through a capacitor whose dielectric is filled with liquid crystal. For example, for a 10 COMMONS×64 SEGMENTS LCD panel, the display controller data buffer will be organized as 10 64-bit registers, as seen in FIG. 2 with reference to user holding buffer 204 and display frame buffer 205.
Therefore, these registers must be multiplexed. The display controller 200 comprises 64×10:1 multiplexer 207. These multiplexers have their select inputs driven by the timing generation module 202 by means of signal 220. Each register of the frame buffer 205 is periodically selected, and the period of selection for each register is called the “frame period.” This frame period depends on the number of commons addressed on the LCD panel and also on other parameters, including the clock frequency divider (division of clock signal 232). The divider circuitry may be contained in the timing generation module 202. This clock frequency divider is not mandatory, but it is common to use a watch crystal oscillator (32.768 KHz) or an on-chip RC oscillator (cheaper than the crystal oscillator) to drive the display circuitry. Since this is a high frequency compared to image display frequency 50 to 100 Hz, there is a need to divide it. The 32.768 KHz clock is used because it comes from a crystal and, therefore, it is very accurate and is often used in other parts (not shown) of the microcontroller, such as the real time clock and periodic interval timer where timing accuracy is mandatory.
The output 225 of multiplexer 207 that is passed through AND gate 206 carries the data to be provided to SEGMENTS terminals of the LCD display panel, but it needs to be processed as it cannot be displayed in that form. This processing is achieved by means of waveform generator 209, which takes into account the type of LCD panel to be addressed. The type of LCD panel to be addressed is configured by user through signal 201 (DISPMODE).
Waveform generator module 209 provides different waveforms according to the data to be displayed (either energized pixel or non-energized, a pixel (or dot) being the area formed by the cross-over of a SEGMENT and a COMMON). The waveform also depends on the time slot location. During a COMMON terminal duration period, one can distinguish 2 different areas. These areas are signaled by timing generation circuitry 202 by means of signal 221.
Waveform generator 209 is a digital module and does not generate the direct waveform that is described in FIG. 4, but rather provides the command selection inputs of the associated analog multiplexers of switch array 203 via line 227. Analog switch array 203 is an array of analog multiplexers (one for each terminal of the LCD display panel) that select among four voltages provided by a resistor ladder 210. Resistor ladder 210 acts as a voltage divider, providing all required voltage values, for example ¾ VDD, ½ VDD, and ¼ VDD for up to 10 common terminals LCD panels, which are carried by signals 226.
Each analog multiplexer of module 203 comprises a selection input driven by the SEGMENT waveform generator 209 for segment terminals 229 via line 227 or the COMMON waveform generator 208 for the common terminals 230 via line 228. COMMON waveform generator 208 may be signaled by timing generation circuitry 202 by means of signal 222. There are analog multiplexers for common terminals 230 and analog multiplexers for segment terminals 229. They are all identical in their intrinsic structure, but their select inputs are not driven the same way to provide the waveforms shown in FIGS. 4 and 5.
FIG. 3 provides the details of a register within the display frame buffer 205 shown in FIG. 2. The display frame buffer contains a set of registers configured to store the data to be displayed on the LCD panel. These registers are organized according to the number of common and segment terminals of the LCD panel. For example, if an LCD panel is organized as 10 COMMONS×64 SEGMENTS, there are 10 registers of 64 bits each. Such a register may be made up of a set of DFFs 305 (one for each data bit, so 64 SEGs=64 DFFs) and an associated set of multiplexers 302 to re-circulate the data in order to store the data.
For each register (in our example, a 64-bit register), the select inputs of multiplexers 302 are connected to the same signal 307 driven by the timing generator module 202 in FIG. 2. When asserted, this signal allows, or enables, the display frame buffer to load the data carried by the user holding register and carried by line 301. The data carried on line 301 passes directly to the output 304 of DFF 305. When signal 307 is de-asserted, the data are re-circulated through multiplexer 302 and its output 303. The DFFs require a clock 306, which is the same for all the DFFs. This clock can be, for example, the same clock signal as the other DFFs of the other modules of the display controller.
The LCD panels do not allow DC current on their terminals. Therefore, a LCD driver must maintain a 0 Volt DC potential across each pixel. The resulting voltage across a pixel is the segment voltage minus the common voltage. If the average resulting voltage is below a particular voltage, the pixel is said to be “non-energized” because it will appear non-visible, whereas if the average voltage across the pixel is greater than the particular voltage, it will appear visible (colored in black in FIGS. 4 and 5).
For simplicity, FIGS. 4-6 show the waveforms for a three COMMON terminals LCD panel. The required specific voltages are ⅓ VDD and ⅔ VDD. Therefore, the resistor ladder will be different from the resistor ladder shown in FIG. 2. Only three resistors of the same value are required instead of four. Only the waveforms of COMMON 0, COMMON 1 and SEGMENT 0 are described. The same explanations apply to other terminals of the LCD display panel. COMMON 0 (COM0) is energized for ⅓ of the frame period. The frame periods are repeated over the time. It must be kept in mind that Vdc voltage must not appear across pixels and that SEGMENTS terminal voltage are propagated across three pixels (one for each common).
FIG. 4 illustrates multiplexed TN LCD waveforms for three COMMONS with one energized pixel. During the time when a common is energized (beginning of frame period for COM0), a toggling waveform is applied on COMMON 0 (COM0). For half the period the voltage is GND, then VLCD is applied. The remaining time in the frame period is composed of switching between ⅔ VLCD and ⅓ VLCD.
The second COMMON 1 (COM 1) is energized on the second part of the frame with the same type of waveform as COMMON 0. This is the same waveform compared to COM0, but right shifted by ⅓ of a frame period. COM2 (not shown) is the same as COM1, but right shifted by ⅓ of a frame period. As would be appreciated by one skilled in the art, the multiplexed mode of operation appears on COMMON terminals.
To get 0 Vdc voltage across pixel COM0-SEG0 when COM0 is energized, if the pixel must be visible (energized), then SEGMENT 0 (SEG0) has the opposite waveform of COM0. Therefore, the first ⅓ of the SEG0 waveform starts with VLCD, followed by GND. If the pixel (COM0-SEG0) must be blanked, i.e., non-energized and non-visible (not shown in FIG. 4), the waveform would start with ⅓ VLCD, then follow with ⅔ VLCD.
In the example of FIG. 4 where only one pixel (SEG0-COM0) is visible and one pixel (SEG0-COM1) is non-visible, the SEG0 waveform of the second ⅓ of the frame period starts with ⅓ VLCD, then follows with ⅔ VLCD. The pixel SEG2-COM0 being also non-visible, the third ⅓ of the frame period is the same as the second ⅓.
The difference of voltages across the pixel SEG0-COM0 is shaped like the third waveform provided in FIG. 4. The root mean square voltage is VON.
For a non-visible pixel like SEG0-COM1, the root mean square voltage is VOFF and is lower than VON, as can be seen in FIG. 4. If the liquid crystal materials used in the display panel are made in a way that VON is higher than the threshold to get full crystals rotation and VOFF is unable to get sufficient crystals rotation, it results in the image displayed in FIG. 4.
FIG. 5 illustrates waveforms for the same type of display panel as in FIG. 4, but having 2 visible pixels. The waveforms of COMMONS are exactly the same as in FIG. 4 because they do not depend on the data to be displayed. However, the SEG0 waveform is slightly different from the SEG0 waveform in FIG. 4. On the second part of the frame period, the SEG0 receives the data for pixel SEG0-COM1. If it must be visible, then this part of the waveform (second ⅓ of the frame period) is the same as the first part, VLCD followed by GND. As a result, the difference of voltage across SEG0-COM0 is different in terms of shape, but remains the same for its root mean square VON and the SEG0-COM1 is modified compared to FIG. 4 and is now VON. Therefore, two pixels are visible.
Some modes of operation can provide capabilities to make the image, or part of the image, blink. These type of modes of operation are well known with respect to electronic appliances that display time, where the second event is materialized by a blinking “:” character, but the time is not blinking.
If the entire image is blinking, then the prior art architecture described in FIG. 2 can be used. Depending on the user configuration programmed in configuration register 211, the blinking frequency information carried on part of signal 201 (LCDBLKFREQ) may be different from 0. Then, timing generation module 202 drives signal 223 with a square waveform. When signal 223 is cleared, the set of AND gates 206 clear data received from display frame buffer 205 and the image is blanked. When not cleared, signal 223 allows the image to be visible, this being the energized period of the blinking period.
The logic to perform this kind of blinking can be very simple with AND gate 206 and square wave signal generation 223. However, in order to have the intermediate voltages as can be seen on the non-energized part of SEG0 in FIG. 6, the resistor ladder must be active, thereby consuming energy. Moreover, the pixels are slightly energized even if they are not visible, which also consumes energy.